1. Field of the Invention
The present invention relates to microprocessors, and more particularly relates to an arrangement for clocking a microprocessor at two different, selectable rates.
2. Background Art
As the speed of semiconductor circuits continues to increase, the speed at which microprocessors are capable of operating has advanced. As a consequence, bus timings have become a critical performance limit of computer system performance. Due to Driver/Receiver delays, and the loading of the external busses, nigh speed bus traffic is difficult to obtain and often costly to implement.
Attempts have been made to resolve this problem and provide increased overall system performance. One approach involves the use of an asynchronous bus-to-processor operation. The processor is allowed to run at a faster internal speed, while the system operates at a slower bus speed. Whenever data is needed to be passed from the internal processor to the slower external system, a hand shaking mechanism is utilized. U.S. Pat. No. 4,807,109, entitled "High Speed Synchronous/Asynchronous Local Bus and Data Transfer Method," which issued to Farrell, et al., and was assigned to Intel Corporation, describes such a scheme. Another approach involves the use of an internal clock that runs at a multiple (2.times., 3.times., etc.) of the external clock.
Both of these approaches have limitations. The asynchronous clock with hand shake approach cannot be utilized to synchronize data from an internal processor to external devices if the processor has an on board cache. The processor would be unable to respond fast enough to keep up with the external busses whenever a bus snoop function was needed. A bus snoop occurs when the external system wants to use the external data bus. When this condition occurs the microprocessor must synchronize to the bus in order to determine if the operation to be performed is the change of a memory location that is in the cache. If this occurs, then the processor must invalidate that cache location. In order to use asynchronous clocking and accommodate this requirement, heretofore it has been necessary to add memory wait states to the system busses. However, these additional wait states are disadvantages in that they can reduce bus performance by 50% or more. In addition, such a hand shake would be required if the microprocessor needed to store data to memory using the bus, or the microprocessor required data that is not in cache (a cache miss), or the microprocessor needed to perform an I/O operation.
Regarding the second approach, limiting the clock speed of the microprocessor to only an integer multiple of the external system clock typically results in the requirement that the system clock be run at a significantly lower speed than it is capable, again adversely effecting overall system performance.
Thus, it is desired to have a solution to the aforementioned problem, permitting faster operation of the microprocessor with respect to the external bus clock, which would not impact the system performance, and yet would still allow the processor to operate at the appropriate speed when using the bus. The present invention provides just such a solution.